Current mirror circuits are widely used in a variety of electronic circuits to copy or scale a reference current. FIG. 1 illustrates a conventional p-channel metal-oxide-semiconductor (PMOS) current mirror circuit 100. Although shown in FIG. 1 and described below with respect to PMOS transistors, the following discussion applies to n-channel metal-oxide-semiconductor (NMOS) current mirror circuits as well. The current mirror circuit 100 includes a first PMOS transistor 110 coupled to a voltage supply providing voltage Vcc. A drain of the PMOS transistor 110 is coupled to a gate and further coupled to a current source 114 that establishes a reference current Iref through the first PMOS transistor. With the gate and drain of the PMOS transistor 110 coupled together, the drain-source voltage Vds and the gate-source voltage Vgs are equal. Additionally, as known, the PMOS transistor 110 is forced into saturation by coupling the gate to the drain. The current mirror circuit 100 further includes a second PMOS transistor 120 coupled to the voltage supply and having a gate coupled to the gate of the first PMOS transistor 110. The PMOS transistor 120 is matched to the PMOS transistor 110, that is, the PMOS transistor 120 has the same transistor characteristics as the PMOS transistor 110. As a result of the gate coupling and matched transistor characteristics, the Vgs of the PMOS transistor 120 is set to the Vgs of the PMOS transistor 110, and consequently, the PMOS transistor 120 conducts an output current lout that is equal to Iref. This can be shown by the equation for drain current Ids of a PMOS transistor in saturation:Ids=(½)μCox(W/L)(Vgs−Vth)2  (1)
With PMOS transistors 110 and 120 matched and Vgs for the two PMOS transistors 110, 120 the same, Iout (i.e., Ids for PMOS transistor 120) will be equal to Iref (i.e., Ids for PMOS transistor 110).
As known, equation (1) is a simplified equation for drain current that does not account for channel length modulation. In MOS transistors having relatively long channel lengths, channel length modulation can be ignored as in equation (1) and provide a good approximation of drain current. However, for transistors having shorter channel lengths, the effect of channel length modulation on drain current Ids becomes more significant, enough so that changes in Vds for a given Vgs can cause variation of the Ids that is unacceptable in applications that rely on a consistent magnitude of current for Iout. In the current mirror circuit 100, as previously discussed, the Vgs of the PMOS 120 is set by the PMOS transistor 110 and current source 114. As previously discussed, if the PMOS 120 has a relatively short channel length, variation in Vds of the PMOS 120 will cause the Iout to vary as well due to channel length modulation. Where it is desirable for Iout to be stable, the variation in Iout may be unacceptable.
The Vds of the PMOS 120 can vary for several reasons, for example, fluctuation of Vcc provided by the voltage supply, changes in operating temperature, and the like. Utilizing transistors for the PMOS transistors 110, 120 having longer channel length can be used to reduce variations in the Ids current due to reduced effect of channel length modulation. The longer channel length transistors, however, occupy greater space on a semiconductor substrate, and can also having decreased response time in comparison to transistors having shorter channel length. Both of these results are generally viewed as undesirable.
Therefore, there is a need for a current mirror circuit that can provide a stable output current when utilized with transistors of different transistor dimensions.